This invention is in the field of integrated circuits, and is more specifically directed to circuits for establishing a reference current within integrated circuits.
The operation of a wide variety of modem integrated circuit functions often relies upon a stable reference level within the integrated circuit. Current-mode circuits have become popular in modem high-performance integrated circuits, because of their inherent higher-speed operation relative to voltage-mode circuits. Accordingly, circuits for generating stable reference currents have recently gained in importance.
It is highly desirable that on-chip-generated reference currents be stable over the operating temperature range of the integrated circuit. Temperature-stable reference currents are conventionally produced by so-called “zero TC” (zero temperature coefficient) reference circuits. The operating principle of zero TC reference circuits commonly relies on compensating a voltage or current that has a positive temperature coefficient (proportional-to-absolute-temperature, or “PTAT”) with a voltage or current that has a negative temperature coefficient (complementary-to-absolute-temperature, or “CTAT”; also referred to as “inverse PTAT”). For example, a voltage corresponding to the difference between the base-emitter voltages of bipolar transistors that conduct dissimilar collector-emitter current densities is proportional to absolute temperature. This PTAT voltage can be added to a voltage that has a negative temperature coefficient (e.g., the base-emitter voltage of a bipolar transistor) to produce a compensated “zero-TC” output current.
FIG. 1 illustrates a conventional zero temperature-coefficient current reference circuit that operates according to this principle. P-n-p bipolar transistor 5 has its emitter at the Vdd power supply voltage, and its base connected to its collector, which is connected to ground (Vss) via resistor 10 and the source-drain path of n-channel MOS transistor 8. P-n-p bipolar transistor 7 also has its emitter at Vdd, and has its collector connected to ground via the source-drain path of n-channel transistor 6. N-channel transistors 6 and 8 conduct the same current as one another, as their gates are connected to the gate of diode-connected n-channel transistor 4 in current mirror fashion, and their channel width-to-length ratios (W/L) are equal. Output transistor 2 similarly has its gate connected in this MOS current mirror, and sinks the output reference current Iref at the open-drain output of the circuit. The base of transistor 7 is connected to node B0 at the other side of resistor 10 from the base and collector of transistor 5. In this conventional circuit, the emitter area of transistor 5 is sized to be N times the emitter area of transistor 7. Node B0 is coupled to the Vdd power supply via resistor 9, which is matched and ratioed to have a resistance that is M times that of resistor 10. The relative sizes of components in the circuit of FIG. 1 are shown by parentheticals, where relevant.
The drain and gate of MOS transistor 4, connected together in diode fashion, is connected to the collector of p-n-p transistor 3, which has its emitter at the Vdd power supply. The base of transistor 3 is connected, at node B2, to the collector of transistor 7 and the drain of transistor 6. Capacitor 11 is connected between node B2 and the Vdd power supply, and serves to increase the power supply rejection ratio (i.e., reduce variations in the output current in response to variations in the Vdd power supply voltage), and to compensate the positive feedback loop in the circuit, as known in the art.
In its steady-state operation, the voltage at node B2, which is at the collector of transistor 7 and the base of transistor 3, will be equal to the voltage at node B0, which is at the base of transistor 7. This voltage matching occurs because the collector-emitter currents conducted by transistors 3 and 7 are forced equal by the current mirror of matched transistors 4 and 6; because transistors 3 and 7 are also matched in size, their collector-emitter current densities are equal to one another, and thus their base-emitter voltages are equal to one another. The temperature stability of this bias condition results from the current at node B0 being established as the sum of a CTAT current (established by the base-emitter voltage of transistor 7, across resistor 9), and a PTAT current defined by the difference in base-emitter voltages of transistors 5, 7 (resulting from their different current densities) impressed across resistor 10. This stable bias point ensures the temperature stability of output reference current Iref, which is the source-drain current of transistor 2.
Error in the operation of the circuit of FIG. 1 is reduced by a factor corresponding to the gain of the amplifier of transistor 3, because of the negative feedback gain loop established by transistors 3, 4, 5, 6, 7, and 8, and resistors 9 and 10. On the other hand, a positive feedback gain loop consisting of transistors 3, 4, 6 and 7 is also present. The circuit is stable so long as the negative feedback loop dominates the positive feedback loop; this condition is assisted by the compensation of the positive feedback loop by capacitor 11. In practice, the circuit of FIG. 1 is typically used in integrated circuits that are constructed by n-well MOS technology, in which case p-n-p bipolar transistors 3, 5, 7 are parasitic devices. The low 0 of these bipolar transistors 3, 5, 7 facilitates stable operation of the circuit, and reduces the size of capacitor 11 that is necessary for adequate compensation.
Modem integrated circuit technology now enables complementary MOS (CMOS) and both bipolar and CMOS devices (BiCMOS) in the same integrated circuit. As a result, current reference circuits that do not rely on parasitic bipolar devices, and that therefore provide higher-precision reference levels, are easily realized. FIG. 2 illustrates a conventional zero-TC current reference circuit realized by p-channel MOS transistors and n-p-n bipolar devices according to this higher capability technology.
In the circuit of FIG. 2, the reference leg includes n-p-n bipolar transistor 15, which has its emitter at Vss and its base and collector connected together. Resistor 16 is connected between this base-collector node and, the drain of p-channel MOS transistor 14, at node X. Transistor 14 has its source at Vdd, and its gate is connected in common with the gates of p-channel MOS transistors 12, 20, 24, 28, each of which has its source also at Vdd. Transistor 12 serves as the output device, and sources output current Iref in open-drain fashion. Transistor 28 has its gate connected to its drain, in diode fashion. N-p-n transistor 29 has its collector connected to the gate-drain node of transistor 28, and its emitter at Vss. Similarly, n-p-n transistor 21 has its collector connected to the drain of transistor 20, and its emitter at Vss; the base of transistor 21 is connected at node X to the drain of transistor 14 and to resistor 16. Resistor 26 is connected between this node X at the base of transistor 21, and ground (Vss). The base of transistor 29 is connected to the drain of transistor 20, at node A, and also to the drain of p-channel transistor 22. Resistor 19 is connected between the drain of transistor 24 (and the gate of transistor 22) and Vss. Compensation capacitor 27 is connected between node A, at the base of transistor 29, and Vss.
Resistors 16, 19, and 26 are typically realized as polysilicon resistors, or alternatively by another resistive material such as thin film or doped silicon. Resistors 16 and 26 are matched and ratioed relative to one another, with resistor 26 having a resistance that is a multiple M times that of resistor 16. For purposes of temperature compensation, as discussed above, transistor 15 has an emitter area that is larger than that of transistors 21, 29 (which are typically matched to one another), by a factor of N.
In its steady-state operation, the conventional circuit of FIG. 2 settles at a bias condition at which the voltage at node A equals the voltage at node X, in this typical situation in which transistors 21, 29 are matched in size. This voltage at nodes A, and X corresponds to the base-emitter voltage of transistors 29 and 21, respectively, because the matched currents conducted by the current mirror of transistors 28 and 20, respectively, ensure equal current densities through transistors 21 and 29. At this bias condition, the current conducted by transistor 28 is mirrored by transistor 14 in the reference leg, and by transistor 12 at the output. As in the case of FIG. 1, because transistor 15 has an emitter area N times that of transistor 21 yet conducting the same current as transistor 21 (by virtue of the mirroring of transistors 14, 20), a positive temperature coefficient base-emitter voltage differential is established across resistor 16. This PTAT current is summed at node X with the CTAT current defined by the base-emitter voltage of transistor 21 that is established across resistor 26. The current at node X in the reference leg thus remains constant over temperature, maintaining the output reference current Iref stable over variations in temperature. In the circuit of FIG. 2, precise operation is facilitated by the amplifier of transistor 29, which establishes a negative feedback loop including transistors 14, 15, 20, 21, 28, and 29, and resistors 16 and 26. On the other hand, a positive feedback loop is established by the loop of transistors 20, 21, 28, and 29. Stability, of course, requires that the negative feedback loop dominate the positive feedback loop in operation.
While the circuit of FIG. 1 typically relied on MOS transistor leakage for startup, the conventional circuit of FIG. 2 includes a positive-feedback startup circuit of transistor 22, in combination with resistor 19 and transistor 24. Prior to startup, no source-drain current is conducted through transistor 28, and thus no mirrored current is conducted by the other MOS devices 20, 24, 12, 14. As the Vdd power supply voltage increases from ground (Vss), p-channel transistor 22 is turned on because its gate is biased to Vss through resistor 19. As Vdd increases to a certain level, transistor 22 provides sufficient base current to transistor 29 to turn it on, which then turns on diode-connected transistor 28. The current through transistor 28 is then mirrored through the other MOS transistors 12, 14, 20, 24. Upon sufficient source-drain current conducted by transistor 24, the gate of transistor 22 will be pulled sufficiently high toward Vdd, turning off transistor 22 and allowing the circuit to settle at its steady-state bias point.
However, n-p-n transistors 15, 21, 29 in this conventional circuit have relatively high β (e.g., on the order of 125), which results in a significant gain in the positive feedback loop of transistors 20, 21, 28, 29. This high loop gain presents a risk that the increasing collector current of transistor 29 will increase the drain-to-source voltage of transistor 28 and undesirably pull the drain of transistor 28 toward Vss, which crashes the collector-emitter voltage of transistor 29 to ground and turns off conduction. The positive feedback startup circuit exacerbates this instability by sensing this state and then turning transistor 22 back on again, which sources base current to transistor 29 that is amplified by its high β, again undesirably increasing the drain-to source voltage of transistor 28. The voltage at node A thus oscillates. While capacitor 27 can theoretically compensate this positive feedback loop to suppress this relaxation oscillation at node A, the size of capacitor 27 required for such compensation is generally too large for efficient implementation in modern integrated circuits. For example, a capacitor 27 of 100 pF (which is approaching the practical limit in modem technology) is inadequate to suppress this relaxation oscillation, in the circuit of FIG. 2 in which transistors 21, 29 have a β of 125. Accordingly, the conventional circuit of FIG. 2 has significant limitations when applied to modern high-performance integrated circuit functions.
As known in the art, current reference circuits that startup from a “constant current” avoid the need to use positive feedback. This is because, in conventional circuits, the constant startup current is injected into only one of the legs of the circuit, thus presenting imbalance in the steady-state bias condition and a corresponding lack of precision in the output reference current. As such, only extremely low levels of constant current can be tolerated in current reference circuits. While JFET devices are ideal for conducting constant low level currents, it is generally too expensive to realize JFETs in modern CMOS and BiCMOS manufacturing process flows, because of the additional process steps that would be necessary. While one could reduce the constant current level by way of a very large resistor, the chip area cost required to realize a polysilicon or diffused resistor of sufficient resistance (on the order of one gigohm) to define a sufficiently low constant current is also prohibitive. In addition, DC power consumption is undesirable in integrated circuits, especially for power-conscious circuits that are used in modern battery-powered digital systems ranging from laptop computers to cellular telephone handsets. As such, conventional current reference circuits in modern, low-power, high-performance, integrated circuits rely on positive feedback startup circuits similar to that of FIG. 2, and must tolerate the potential for instability presented by the oscillating node.